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Tuesday, 18 Dec 2018

Dr. ARVIND RAJAWAT

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Dr. Arvind Rajawat

Dr. ARVIND RAJAWAT

Designation

 

  Professor & HOD

Address 
Phone
E-mail

Department of ECE, MANIT Bhopal -462003 (M.P.) India
0755-4051510(Office)
rajawata[at]manit[dot]ac[dot]in,

Date of Birth

December-01-1969

Educational Qualification

 PhD, M.E., B.E.

Experience

Working as Regular faculty member at MANIT since 1991 21 Years

Specialization

Embeded System Design, Hardware Software Codesign, VLSI Design

Publication
  • International Journals        11 (Scopus/SCI/SCIE)
  • National Journal
  •  National Conference            
  • International Conference   06 (Scopus)

                                                              Total Published Paper : - 17 (Scopus/SCI/SCIE)

Member of professional bodies
  • ISTE
  • IETE

Country Visited

France
Number of P.G. Projects guided

20 PG Dissertations  supervised

Project/ Consultancy undertaken
  • Chief Investigator SMDP-C2SD Project from MEITY
  • Infrastructure development for Embedded System Design Center
Administrative work done
  • Worked as Senior Warden, Chairman Council of Warden, Professor In-charge Legal Cell, Proctor, HoD
Publications (Till July 2018)
In Journals
  1. Vaibhav Sharma, Arvind Rajawat, “Review of Approaches for Radiation Hardened Combinational Logic in CMOS Silicon Technology”, IETE Technical Review, Published online 21 June 2018, DOI: 10.1080/02564602.2017.1343689.
  2. Abhishek N. Tripathi, Arvind Rajawat, “Fast and efficient power estimation model for FPGA based designs”, Microprocessors and Microsystems, Vol. 59, 2018, pp 37-45.
  3. Rachna Singh, Arvind Rajawat, Analytical Model for High-Level Area Estimation of FPGA Design”, International Journal of Embedded and Real-Time Communication Systems, Vol 7, Issue 2, July 2016, pp 35-44.
  4. Rachna Singh, Arvind Rajawat, “Accurate area estimation model for FPGA based Implementation”, IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 6, Issue 4, Ver. II (Jul. - Aug. 2016), e-ISSN: 2319 – 4200, p-ISSN: 2319 – 4197, pp. 26- 32.
  5. Mahendra Vucha, Arvind Rajawat, “Dynamic Task Distribution Model for On-Chip Reconfigurable High Speed Computing System”, International Journal of Reconfigurable Computing, Volume 2015, Article ID 783237 (Open Access Journal, Hindawi Publishing Corporation).
  6. Mahendra Vucha, Arvind Rajawat, “A Novel Methodology For Task Distribution In Heterogeneous Reconfigurable Computing System”, International Journal of Embedded Systems and Applications (IJESA) Vol.5, No.1, March 2015, pp. 19-39.
  7. Nishant Kumar, Ekta Aggrawal and Arvind Rajawat, “Dynamically scalable dual-core pipelined processor”, International Journal of Electronics, Volume 102, Issue 10, 2015, pp. 1754-1764.
  8. Mahendra Vucha, Arvind Rajawat, “A Case Study: Task Scheduling Methodologies for High Speed Computing Systems”, International Journal of Embedded systems and Applications (IJESA) Vol.4, No.4, December 2014, pp. 1-12
  9. Rajendra Patel, Arvind Rajawat, “Recent Trends in Embedded System Software Performance Estimation”, Journal of Design Automation for Embedded System, Springer, January 2014. (Published online: 4th January 2014, Volume No. 17, Issue 1, pp. 193-213, 2013.
  10. Rajendra Patel, Arvind Rajawat, “Dominant Block Guided Optimal Cache Size Estimation to Maximize IPC of Embedded Software”, International Journal of Embedded Systems and Applications (IJESA), Vol. 3, No. 3, September 2013, pp. 35- 44.
  11. Rachna Singh, Arvind Rajawat, “A Review of FPGA-based design methodologies for efficient hardware Area Estimation”, in IOSR Journal of Computer Engineering (IOSR-JCE), Vol. 13, Issue 4, May 2013, pp 1-6.
In International Conferences
  1. Disha Yadav, Arvind Rajawat, “Area and throughput analysis of different AES architectures for FPGA implementations”, Proceedings of International Symposium on Nanoelectronic and Information Systems, (iNIS 2016), 19-21 December 2016, Gwalior, India, pp. 67-71.
  2. Vaibhav Sharma, Arvind Rajawat, “Performance evaluation of circuit level approaches for radiation hardened primitive gates”, Proceedings of International Conference on Advances in Computing, Communications and Informatics (ICACCI 2016), 21-24 September 2016, Jaipur, India, pp 1811-1815.
  3. Rajendra Patel, Arvind Rajawat, “Instruction Cache Design Space Exploration for Embedded Software Applications”, 19th International Symposium on VLSI Design and Test, (VDAT 2015), Ahmedabad, June 26-29, 2015, pp. 1-5.
  4. Mahendra Vucha, Arvind Rajawat, “An effective dynamic scheduler for reconfigurable high speed computing system”, IEEE International Advance Computing Conference, (IACC 2014), Gurgaon, Feb 21-22, 2014, pp. 766-773.
  5. Rajendra Patel, Arvind Rajawat, R. N. Yadav, “Remote access of peripherals using web server on FPGA platform”, International Conference on Recent Trends inInformation, Telecommunication, and Computing (ITC 2010), Kochi, Kerala March 12-13, pp. 274-276.
  6. Arvind Rajawat, M. Balakrishnan, Anshul Kumar, “Interface Synthesis: Issues and Approaches”, Proceedings of the 13th International Conference on VLSI Design, January 3-7, 2000, Calcutta, India, pp. 92-97.
Any other information 4 PhD supervised